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Thursday, 10 January 2013
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[VUSR] 66181 CS501 QUIZ NO.3 DATED JAN 10, 2013
CS501 Advance Computer Architecture
Quiz No.3 JAN 10,2013
_________ is a technique in which some of the CPU's address lines forming an input to the address decoder are ignored.
Microprogramming
Instruction pre-fetching
Pipelining
Partial Decoding
An Interface that can be used to connect the microcomputer bus to ______________ is called an I/O port
Flip flops
Memory
Peripherals devices
Multiplexes
Connection to a CPU that provides a data path between the CPU and external devices, such as a keyboard, display, or reader is called-----------
Buffer
I/O port
Memory mapping
Processor
In which one of the following methods for resolving the priority, the device with the highest priority is placed in the first position, followed by lower-priority devices up to the device with the lowest priority which is placed last in the series?
Asynchronous
Daisy-Chaining Priority
Parallel
Semi-synchronous
Identify the type of serial communication error condition in which A 0 is received instead of a stop bit (which is always a 1)?
Framing error
Parity error
Overrun error
Under-run error
Where does the processor store the address of the first instruction of the ISR?
Interrupt vector
Interrupt request
Interrupt handler
All of the given Options
Identify the following type of serial communication error condition: "The prior character that was received was not still read by the CPU and is over written by a new received character."
Framing error
Parity error
Overrun error
Under-Run error
In ____________ a separate address space of the CPU is reserved for I/O operations
Isolated I/O
Memory Mapped I/O
All of the above
None of above
Every time you press a key, an interrupts is generated. This is an example of
Hardware Interrupt
Software Interrupt
All of the given
None of the given
_________ is an electrical pathway through which the processor communication with the internal and external devices attached to the computer.
Computer Bus
Hazard
Memory
Disk
Where does the processor store the address of the first instruction of the ISR?
Select correct option:
Interrupt vector
Interrupt request
Interrupt handler
All of the given options
In ________, a separate address space of the CPU is reserved for I/O operations.
Select correct option:
Isolated I/O
Memory Mapped I/O
All of above
None of above
-------------- is the time needed by the CPU to recognize (not service) an interrupt request.
Select correct option:
Interrupt Latency
Response Deadline
Timer delay
Throughput
Question # 4
_________ is a technique in which some of the CPU's address lines forming an input to the address decoder are ignored.
Select correct option:
Microprogramming
Instruction pre-fetching
Pipelining
Partial decoding
Question # 5
How can you define an interrupt?
Select correct option:
A process where an external device can speedup the working of the microprocessor
A process where memory can speed up programs execution speed
A process where an external device can get the attention of the microprocessor
A process where input devices can takeover the working of the microprocessor
Question # 6
An interface that can be used to connect the microcomputer bus to ________is called an I/O Port.
Select correct option:
Flip Flops
Memory
Peripheral devices
Multiplexers
Question # 7
Every time you press a key, an interrupt is generated. This is an example of
Select correct option:
Hardware interrupt
Software interrupt
All of the given
None of the given
Question # 8
Identify the following type of serial communication error condition: "The prior character that was received was not still read by the CPU and is over written by a new received character."
Select correct option:
Framing error
Parity error
Overrun error
Under-run error
Question # 9
A software routine performed when an interrupt is received by the computer is called as ---------
Select correct option:
Interrupt
Interrupt handler
Exception
Trap
Which one of the following methods for resolving the priority makes use of individual bits of a priority encoder?
Select correct option:
Daisy-Chaining Priority
Asynchronous Priority
Parallel Priority
Semi-synchronous Priority
In which one of the following methods for resolving the priority, the device with the highest priority is placed in the first position, followed by lower-priority devices up to the device with the lowest priority, which is placed last in the series?
Select correct option:
Asynchronous
Daisy-Chaining Priority
Parallel
Semi-synchronous
In ________, a separate address space of the CPU is reserved for I/O operations.
Select correct option:
Isolated I/O
Memory Mapped I/O
All of above
None of above
Identify the following type of serial communication error condition: "The prior character that was received was not still read by the CPU and is over written by a new received character."
Select correct option:
Framing error
Parity error
Overrun error
Under-run error
Identify the following type of serial communication error condition in which no character is available at the beginning of an interval.
Select correct option:
Framing error
Parity error
Overrun error
Under-run error
Which one of the following methods for resolving the priority makes use of individual bits of a priority encoder?
Select correct option:
Daisy-Chaining Priority
Asynchronous Priority
Parallel Priority
Semi-synchronous Priority
A software routine performed when an interrupt is received by the computer is called as ---------
Select correct option:
Interrupt
Interrupt handler
Exception
Trap
_________ is a technique in which some of the CPU's address lines forming an input to the address decoder are ignored.
Select correct option:
Microprogramming
Instruction pre-fetching
Pipelining
Partial decoding
Identify the type of serial communication error condition in which A 0 is received instead of a stop bit (which is always a 1)?
Select correct option:
Framing error
Parity error
Overrun error
Under-run error
Where does the processor store the address of the first instruction of the ISR?
Select correct option:
Interrupt vector
Interrupt request
Interrupt handler
All of the given options
Which one of the following is NOT a technique used when the CPU wants to exchange data with a peripheral device?
Select correct option:
Direct Memory Access (DMA)
Interrupt driven I/O
Programmed I/O
Virtual Memory
A software routine performed when an interrupt is received by the computer is called as ---------
InterruptC
Interrupt handler
Exception
Trap
Which one of the following methods for resolving the priority makes use of individual bits of a priority encoder?
Daisy-Chaining Priority
Asynchronous Priority
Parallel Priority
Semi-synchronous Priority
-------------- is the time needed by the CPU to recognize (not service) an interrupt request.
Interrupt Latency
Response Deadline
Timer delay
Throughput
______ is an electrical pathway through which the processor communicates with the internal and external devices attached to the computer.
Computer Bus
Hazard
Memory
Disk
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[VUSR] 66180 CS401 QUIZ NO.3 JAN 10, 2013
CS401- Computer Architecture and Assembly Language
Quiz No.2 JAN 10, 2013
Question # 1 of 10 ( Start time: 02:24:57 PM ) Total Marks: 1
Memory address space is selected when which of the following instructions is given to the processor?s
Select correct option:
MOV
DEC
IN
ADD
PCB stands for?
Select correct option:
Process Control Block
Process Clearing Block
Programable Counter Block
Programs Control Block
Question # 3 of 10 ( Start time: 02:26:41 PM ) Total Marks: 1
Creation of threads can be
Select correct option:
Static
Dynamic
Both
None
Threads can have function calls, parameters and ________ variables.
Select correct option:
global
local
legal
illegal
Which of the following is the highest priority interrupt
Int3
Int2
Int1
Int0
The input frequency of the programmable interval timer (PIT) is
Fixed
Depends on processor clock
Variable
Depends on hardware attached
Programmable interrupt controller has two ports 20 and 21. Port 20 is the control port while port 21 is...........
The Interrupt mask register
Interrupt port
Output port
Input port
The source registers in OUT is ?
AL or AX
BL or BX
CL or CX
DL or DX
The time interval between two timer ticks is ?
40ms
45ms
50ms
55ms
Which of the following interrupts is used for saving and restoring the registers
INT6
Int7
Int8
Int0
In programmable interrupt controller which of the following ports is referred as a interrupt mask register?
19
20
21
22
Refernce:- page no 115
Port 21 is the interrupt mask register which can be used
for selectively enabling or disabling interrupts
The thread registration code initializes the PCB and adds it to the linked list so that the __________ will give it a turn.
Assembler
Scheduler
Linker
Debugger
The programmable interval timer (PIT) has input frequency of
1.193MHZ
2.192MHZ
3.196MHZ
4.198MHZ
Peripheral address space is selected when which of the following instructions is given to the processor?
MOv
In
Add
Out
Direction flag, the interrupt flag, and the trap flag are
used for mathematical operations
not used for mathematical operations
status flags
not status flags
An End of Interrupt (EOI) signal is sent by
Handler
Processor
IRQ
PIC
The space where all the registers of a task are stored is called the
control block
process control block
stack
memory
The number of pins in a parallel port connector are?
Select correct option:
20
25
30
35
Which of the following interrupt is of highest priority interrupt?
Select correct
Key board interrupt
Timer interrupt
INT 2
INT 3
The instruction used to read a character from the keyboard port is
in al, 0x60
out al, 0x60
in al, 0x80
out al, 0x80
Each thread can have their own
execution area
stack
memory
array
All the registers & stack are saved in
Multitasking
multi-processing
function call
BIOS
Which of the following IRQs is used for sound card or network card?
IRQ 4
IRQ 5
IRQ 6
IRQ 7
In programmable interrupt controller which of the following ports is referred as a control port?
22
19
21
20
In programmable interrupt controller which of the following ports is used for selectively enabling or disabling interrupts ?
19
20
21
22
Which of the following is the highest priority interrupt
Int3
Int2
Int1
Int0
The input frequency of the programmable interval timer (PIT) is
Fixed
Depends on processor clock
Variable
Depends on hardware attached
Programmable interrupt controller has two ports 20 and 21. Port 20 is the control port while port 21 is...........
The Interrupt mask register
Interrupt port
Output port
Inpuit port
The source registers in OUT is ?
AL or AX
BL or BX
CL or CX
DL or DX
Creation of threads can be
Static
Dynamic
Both
None
The time interval between two timer ticks is ?
40ms
45ms
50ms
55ms
Which of the following interrupts is used for saving and restoring the registers
INT6
Int7
Int8
Int0
PCB stands for?
Process Control Block
Process Clearing Block
Programable Counter Block
Programs Control Block
In programmable interrupt controller which of the following ports is referred as a interrupt mask register?
19
20
21
22
The thread registration code initializes the PCB and adds it to the linked list so that the __________ will give it a turn.
Assembler
Scheduler
Linker
Debugger
The programmable interval timer (PIT) has input frequency of
1.193MHZ
2.193MHZ
3.193MHZ
4.193MHZ
Threads can have function calls, parameters and __________ variables.
Global
Local
Legal
Illegal
Peripheral address space is selected when which of the following instructions is given to the processor?
MOv
In
Add
Out
Direction flag, the interrupt flag, and the trap flag are
used for mathematical operations
not used for mathematical operations
status flags
not status flags
An End of Interrupt (EOI) signal is sent by
Handler
Processor
IRQ
PIC
The space where all the registers of a task are stored is called the
control block
process control block
stack
memory
The instruction used to read a character from the keyboard port is
in al, 0x60
out al, 0x60
in al, 0x80
out al, 0x80
Which of the following pins of a parallel port connector are grounded?
25-32
10-18
18-25
32-39
Each thread can have their own
execution area
stack
memory
array
All the registers & stack are saved in
Multitasking (page 139)
multi-processing
function call
BIOS
Question # 1 of 10 ( Start time: 02:58:14 PM ) Total Marks: 1
The instruction used to read a character from the keyboard port is
Select correct option:
in al, 0x60
out al, 0x60
in al, 0x80
out al, 0x80
Question # 2 of 10 ( Start time: 02:59:00 PM ) Total Marks: 1
Each thread can have their own
Select correct option:
execution area
stack
memory
array
Question # 3 of 10 ( Start time: 03:00:28 PM ) Total Marks: 1
There is no instruction to clear the
Select correct option:
Trap flag
Interrupt flag
Direction flag
None of the above
Question # 4 of 10 ( Start time: 03:01:36 PM ) Total Marks: 1
PCB stands for?
Select correct option:
Process Control Block
Process Clearing Block
Programable Counter Block
Programs Control Block
From the following which is related to read a char from key board?
Select correct option:
out al, 0x60
in al, 0x60
out dx, al
ou dx, 0x378
The input frequency of the programmable interval timer (PIT) is
Select correct option:
Fixed
Depends on processor clock
Variable
Depends on hardware attached
The thread registration code initializes the PCB and adds it to the linked list so that the __________ will give it a turn.
Select correct option:
Assembler
Scheduler
Linker
Debugger
Question # 8 of 10 ( Start time: 03:02:37 PM ) Total Marks: 1
The source registers in OUT is ?
Select correct option:
AL or AX
BL or BX
CL or CX
DL or DX
Question # 9 of 10 ( Start time: 03:03:11 PM ) Total Marks: 1
The time interval between two timer ticks is ?
Select correct option:
40ms
45ms
50ms
55ms
Creation of threads can be
Select correct option:
Static
Dynamic
Both
None
Memory address space is selected when which of the following instructions is given to the processor?s
Select correct option:
MOV
DEC
IN
ADD
Question # 2 of 10 ( Start time: 02:25:56 PM ) Total Marks: 1
PCB stands for?
Select correct option:
Process Control Block
Process Clearing Block
Programable Counter Block
Programs Control Block
Question # 3 of 10 ( Start time: 02:26:41 PM ) Total Marks: 1
Creation of threads can be
Select correct option:
Static
Dynamic
Both
None
Question # 4 of 10 ( Start time: 02:27:46 PM ) Total Marks: 1
Threads can have function calls, parameters and ________ variables.
Select correct option:
global
local
legal
illegal
Which of the following is the highest priority interrupt
Int3
Int2
Int1
Int0
The input frequency of the programmable interval timer (PIT) is
Fixed
Depends on processor clock
Variable
Depends on hardware attached
Programmable interrupt controller has two ports 20 and 21. Port 20 is the control port while port 21 is...........
The Interrupt mask register
Interrupt port
Output port
Input port
The source registers in OUT is ?
AL or AX
BL or BX
CL or CX
DL or DX
The time interval between two timer ticks is ?
40ms
45ms
50ms
55ms
Which of the following interrupts is used for saving and restoring the registers
INT6
Int7
Int8
Int0
In programmable interrupt controller which of the following ports is referred as a interrupt mask register?
19
20
21
22
The thread registration code initializes the PCB and adds it to the linked list so that the __________ will give it a turn.
Assembler
Scheduler
Linker
Debugger
The programmable interval timer (PIT) has input frequency of
1.193MHZ
2.192MHZ
3.196MHZ
4.198MHZ
Peripheral address space is selected when which of the following instructions is given to the processor?
MOv
IN
Add
Out
Direction flag, the interrupt flag, and the trap flag are
used for mathematical operations
not used for mathematical operations
status flags
not status flags
An End of Interrupt (EOI) signal is sent by
Handler
Processor
IRQ
PIC
The space where all the registers of a task are stored is called the
control block
process control block
stack
memory
Question # 3 of 10 ( Start time: 12:20:27 AM ) Total Marks: 1
The number of pins in a parallel port connector are?
Select correct option:
20
25
30
35
Which of the following interrupt is of highest priority interrupt?
Select correct
option:
Key board interrupt
Timer interrupt
INT 2
INT 3
The instruction used to read a character from the keyboard port is
in al, 0x60
out al, 0x60
in al, 0x80
out al, 0x80
Each thread can have their own
execution area
stack
memory
array
Refernce:-
All the registers & stack are saved in
Multitasking
multi-processing
function call
BIOS
Which of the following is the highest priority interrupt
Select correct option:
INT3
INT2
INT1
INT0
Which of the following interrupts is used for saving and restoring the registers
Select correct option:
INT6
INT7
INT8
INT0
There is no instruction to clear the
Select correct option:
Trap flag
Interrupt flag
Direction flag
None of the above
For the external hardware to generate an interrupt there are how many pins out side the processor?
1
2
3
4
Which of the following IRQs is derived by a keyboard?
IRQ 0
IRQ 1
IRQ 2
IRQ 3
Which of the following IRQs is connected to serial port COM 2?
Select correct option:
IRQ 0
IRQ 1
IRQ2
IRQ3
Programmable interrupt controller (PIC) has
Select correct option:
One input signals and eight output signals
One input signal and one output signal not sure
Eight input signals and one output signals
Eight input signals and eight output signals
Which of the following IRQs is used by the parallel port?
IRQ 5
IRQ 4
IRQ 6
IRQ 7
Which of the following IRQs is a cascading interrupt?
IRQ 0
IRQ 1
IRQ 2
IRQ 3
Which of the following pins of a parallel port connector are grounded
10-15
18-25
25-32
32-39
Which of the following IRQs is used for Floppy disk derive?
IRQ 4
IRQ 5
IRQ 6
IRQ 7
When two devices in the system want to use the same IRQ line then what will happen?
A) An IRQ Collision
B) An IRQ Conflict
C) An IRQ Crash
D) An IRQ Blockage
The parallel port connector is called ?
Select correct option:
DB-25
BD-25
DB-24
BD-24
IRQ is referred to
Select correct option:
Eight input signals
One output signal
Eight output signals
One input signals
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